Delay signal generator and recording pulse generator

ABSTRACT

A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A delay circuit delays delay subject signals by a predetermined amount to generate delay signals. A delay amount for the delay circuit is controlled by a delay amount control circuit. A logic circuit generates a recording pulse by logically synthesizing the delay signals. The delay amount control circuit includes a voltage controlled oscillator formed by connecting, in a ring-like manner, a plurality of delay elements having the same configuration as the delay elements included in the delay circuit. An output signal of the voltage controlled oscillator is locked at a point where a delay amount for each delay element becomes a fraction of an integer of one cycle of a reference clock signal.

FIELD OF THE INVENTION

The present invention relates to a delay signal generator that iscapable of generating, for a single input signal, a plurality ofdiffering delay signals having different minimum units of delay amounts,and to a recording pulse generator that is capable of retrievingmodulated data, which has been subjected to predetermined modulation,and generating recording pulses for at least two different disc media.

BACKGROUND ART

A data recorder, which records desired data using a laser on a discmedium functioning as a recording medium, such as an optical disc,usually includes a write strategy circuit. The write strategy circuitgenerates a timing signal for controlling the state of laserirradiation. One example of such a timing signal is a recording pulse,which is generated by pulse-modulating data subject to recording, forcontrolling the intensity and time of laser irradiation on a discmedium. The laser irradiation is carried out according to the recordingpulse so that pits corresponding to the desired data in an optimalmanner are formed on the disc medium.

A timing signal, such as a recording pulse, is generated, its unit beinga time interval that is shorter than the cycle of a reference clocksignal. The reference clock signal is a clock signal corresponding tothe rotation mode of the disc medium and serves as a reference for therecording operation. The write strategy circuit generates a plurality ofdelay signals, each having a predetermined delay with respect to an edgeof the reference clock signal. By using such delay signals, the writestrategy circuit generates a timing signal, its unit being a timeinterval shorter than the cycle of the reference clock signal, forcontrolling the mode of laser irradiation.

In recent years, various disc media, such as CD-R (CompactDisc-Recordable), CD-RW (Compact Disk-Rewritable), DVD-R (DigitalVersatile Disc-Recordable), and DVD-RW (Digital VersatileDisc-Rewritable), have appeared on the market. Under such circumstances,there has been a demand for versatile recording controllers andreproduction controllers for controlling recording and reproduction ofdata on plural types of disc media, such as a CD-R and a DVD-R. However,such recording controllers and reproduction controllers cannot beconstructed without a substantial increase in their circuit scale.

The specification relating to control of the laser irradiation statediffers for each type of disc medium. This enlarges the circuit scale ofthe write strategy circuit. To be more specific, the write strategycircuit generates a timing signal whose time interval differs dependingon the specification for each disc medium. To this end, the writestrategy circuit is required to include a separate delay circuit foreach specification in order to generate a delay signal corresponding toeach specification. This inevitably enlarges the circuit scale of thewrite strategy circuit.

The above-described problem is not limited to the write strategycircuit, but commonly occurs with any delay signal generator thatgenerates, from a single input signal, a plurality of delay signalsdiffering from one another in the minimum unit of delay amount.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a delaysignal generator and a recording pulse generator that optimally suppressan increase in their circuit scales even when generating, for a singleinput signal, a plurality of delay signals differing from one another inthe minimum unit of delay amounts.

To achieve the above object, a first aspect of the present invention isa delay signal generator provided with a delay circuit for delaying aninput signal in a stepped manner and including a plurality ofseries-connected first delay elements, each controlling a delay amountin accordance with a control voltage. A delay amount control circuit,connected to the delay circuit, generates the control voltage andsupplies the plurality of first delay elements with the control voltage.A selector, connected to the delay circuit, selects an output of one ofthe plurality of first delay elements and generates a delay signal witha predetermined delay amount. The delay amount control circuit includesa voltage controlled oscillator having a plurality of second delayelements connected in a ring-like manner. The second delay elements eachhave the same configuration as the first delay elements, and thequantity of the second delay elements is based on the quantity of thefirst delay elements. A first frequency divider, connected to thevoltage controlled oscillator, divides the frequency of an output signalof the voltage controlled oscillator by a first frequency dividing ratioto generate a first frequency-divided signal. A second frequency dividerdivides the frequency of a predetermined reference clock signal by asecond frequency dividing ratio to generate a second frequency-dividedsignal. A phase comparator, connected to the first and second frequencydividers, compares a phase of the first frequency-divided signal and aphase of the second frequency-divided signal to generate a comparisonsignal. A filter circuit, connected to the phase comparator, generatesthe control voltage in response to the comparison signal. The delayamount control circuit changes the delay amount for one of the firstdelay elements included in the delay circuit by changing a frequencydividing ratio rate that is a ratio of the second frequency dividingratio relative to the first frequency dividing ratio.

A second aspect of the present invention is a recording pulse generatorfor retrieving modulated data that has been subjected to a predeterminedmodulation process and generating recording pulses for at least two discmedia that differ from each other. The recording pulse generator isprovided with a plurality of delay circuits, each of which delays aninput signal in a stepped manner, includes a plurality ofseries-connected first delay elements, and controls a delay amount inaccordance with a control voltage. A delay amount control circuit,connected to the plurality of delay circuits, generates the controlvoltage and supplying the plurality of first delay elements included ineach delay circuit with the control voltage. A plurality of selectorsare each connected in correspondence with one of the plurality of delaycircuits. Each of the selectors selects an output of one of theplurality of first delay elements included in the corresponding delaycircuit and generates a delay signal with a predetermined delay amount.A logic circuit, connected to the plurality of selectors, logicallysynthesizes the delay signal of each selector to generate a recordingpulse. The delay amount control circuit changes a delay amount for oneof the first delay elements included in each delay circuit by changingthe control voltage.

The delay amount control circuit is provided with a voltage controlledoscillator including a plurality of second delay elements, each havingthe same configuration as the first delay elements and being connectedin a ring-like manner. The quantity of the second delay elements isbased on the quantity of the first delay elements. A first frequencydivider, connected to the voltage controlled oscillator, divides thefrequency of an output signal of the voltage controlled oscillator by afirst frequency dividing ratio and generates a first frequency-dividedsignal. A second frequency divider divides the frequency of apredetermined reference clock signal by a second frequency dividingratio and generates a second frequency-divided signal. A phasecomparator, connected to the first and second frequency dividers,compares a phase of the first frequency-divided signal and a phase ofthe second frequency-divided signal to generate a comparison signal. Afilter circuit, connected to the phase comparator, generates the controlvoltage in response to the comparison signal. The delay amount controlcircuit changes the delay amount for one of the first delay elementsincluded in each delay circuit by changing a frequency dividing ratiorate that is a ratio of the second frequency dividing ratio relative tothe first frequency dividing ratio.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing the entire configuration ofa write strategy circuit according to a preferred embodiment of thepresent invention;

FIG. 2 is a schematic block diagram showing the configuration of a delaysignal generation circuit included in the write strategy circuit of thepreferred embodiment;

FIG. 3 is a circuit diagram showing the configuration of a delay elementin the preferred embodiment; and

FIG. 4 is a timing chart showing a generation mode of a recording pulsein the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A recording pulse generator according to a preferred embodiment of thepresent invention applied to a write strategy circuit for CDs and DVDswill now be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data recordingcontroller, including the write strategy circuit, and its peripheralcircuits.

In FIG. 1, an optical disc 1, which is controlled to be rotated with aconstant linear velocity by a spindle motor 10, is a CD (CD-R or CD-RW)or a DVD (DVD-R or DVD-RW). On the optical disc 1, regardless of whetherit is a CD or a DVD, a single spiral track is formed as a data recordingarea. The track is formed by creating a groove in a flat surface (land)of the disc.

When the optical disc 1 is a CD, the groove is slightly wobbled.Information called ATIP (Absolute Time In Pregroove) is recorded where acycle change occurs in the wobble of the groove. By tracing the track toread the ATIP information written in the wobble of the groove, absolutetime information of the present track position can be obtained.

When the optical disc 1 is a DVD, a groove is also slightly wobbled.However, the wobble of the groove does not necessarily include addressinformation. A DVD has, in addition to wobbles, areas called “landprepits (LPP)”, which include positional information on the disc medium,at predetermined intervals on the track.

The data recording controller 100 retrieves data stored in a DRAM (notshown), generates a recording pulse corresponding to the retrieved data,and outputs the recording pulse to an optical head 20. A control unit 30is included in a data recorder on which the data recording controller100 is mounted and is a microcomputer for controlling each unit of thedata recorder. According to the type of the optical disc 1, the controlunit 30 outputs specification information relating to data recordingcontrol to the data recording controller 100.

The data recording controller 100 will now be described in more detail.

A clock generation circuit 110 generates different reference clocksignals CLK depending on whether the optical disc 1 is a CD or a DVD.The reference clock signal CLK is an operation clock signal for the datarecording controller 100. To generate such a different reference clocksignal CLK, the clock generation circuit 110 includes an oscillator 111and a PLL circuit 112.

The oscillator 111 is a circuit for generating an operation clock signalused by the data recording controller 100 to control recording of dataonto a CD, which serves as the optical disc 1. The oscillator 111 isformed by, for example, a crystal oscillator.

The PLL circuit 112 is a circuit for generating an operation clocksignal used by the data recording controller 100 to control recording ofdata onto a DVD, which serves as the optical disc 1. The PLL circuit 112generates a clock signal CLK based on an LPP signal and a wobble signaloutput from the optical head 20. To be more specific, when retrieving awobble signal and generating a clock signal with a predeterminedfrequency, the PLL circuit 112 further retrieves an LPP signal andfinely adjusts the frequency to generate a clock signal CLK. The PLLcircuit 112 may be one that is described in, for example, JapanesePatent Application Nos. 2000-028159, 2000-038193, and 2000-049702.Further, the PLL circuit 112 may generate a clock signal CLK based oneither a wobble signal or an LPP signal.

A command signal (CD/DVD mode switching signal) issued by the controlunit 30 determines which one of a clock signal output from theoscillator 111 and a clock signal output from the PLL circuit 112 isused as the reference clock signal CLK to be output from the clockgeneration circuit 110.

A DVD encoder 120 performs 8 to 16 bits modulation in compliance withthe DVD data format on data input from the DRAM (not shown). The DVDencoder 120 operates in accordance with the reference clock signal CLKgenerated by the clock generation circuit 110.

A CD encoder 130 performs 8 to 14 bits modulation in compliance with theCD data format on data input from the DRAM (not shown). The CD encoder130 also operates in accordance with a reference clock signal CLKgenerated by the clock generation circuit 110.

The data modulated by the DVD encoder 120 and the data modulated by theCD encoder 130 are both input into a selector 140. The selector 140selectively outputs the data modulated by the DVD encoder 120 or thedata modulated by the CD encoder 130. In more detail, the selector 140includes a register 141 for storing information that designates the datathat is to be output from the modulated data. When informationindicating whether the optical disc 1 is a CD or a DVD, or informationdesignating the desired data, is written to the register 141 by thecontrol unit 30, the selector 140 selects an output signal according tothe written information.

The modulated data to be selectively output from the selector 140 isretrieved in a write strategy circuit 150 as data that ispulse-modulated to a recording pulse for controlling the output of laserthat irradiates the optical disc 1. The write strategy circuit 150generates a recording pulse based on the modulated data and outputs therecording pulse to the optical head 20.

In more detail, the write strategy circuit 150 includes a first circuit151, which generates various signals used to generate a recording pulsebased on the modulated data and the reference clock signal CLK, and asecond circuit 152, which generates a recording pulse based on thevarious signals.

The first circuit 151 generates the following three signals:

a delay subject signal, which is a signal subject to delay in the secondcircuit 152;

a delay amount setting signal, which is a signal for setting a delayamount by which the delay subject signal is delayed in the secondcircuit 152; and

a clock synchronization signal, which is a signal used, together with adelay signal generated in the second circuit 152 based on the delaysubject signal, to generate a recording pulse. The clock synchronizationsignal is a pulse signal that rises or falls in synchronization with therising edges of the reference clock signal CLK.

The generation mode for the delay subject signal, the delay amountsetting signal, and the clock synchronization signal in the firstcircuit 151 changes according to the specification relating to datarecording on the optical disc 1, that is, according to the specificationof the recording pulse. To be more specific, the generation mode of thesignals is changed according to whether the optical disc 1 is a CD or aDVD.

In more detail, the first circuit 151 includes a register 151 a forstoring table data defining the pulse modulation mode of modulated data,that is, table data defining the pulse modulation mode of data that isto be pulse-modulated. The pulse modulation mode, that is, thegeneration mode of the delay subject signal, the delay amount settingsignal, and the clock synchronization signal, is changed based on thetable data.

The table data is written into the register 151 a by the control unit30.

The second circuit 152 generates the delay signal by adding a delayamount designated by a delay amount setting signal to the delay subjectsignal, and generates the recording pulse based on the delay signal andthe clock synchronization signal.

A delay signal generation circuit 200, which is included in the secondcircuit 152, for generating the delay signal by adding the delay amountdesignated by the delay amount setting signal to the delay subjectsignal, will now be described with reference to FIG. 2.

FIG. 2 shows the delay signal generation circuit 200 and a logic circuit300 for generating a recording pulse by logically synthesizing delaysignals and the clock synchronization signal. The delay signalgeneration circuit 200 and the logic circuit 300 are both included inthe second circuit 152.

As shown in FIG. 2, the delay signal generation circuit 200 generatesfour delay signals (delay signals D1 to D4) by adding the delay amountdesignated by the delay amount setting signal to four different delaysubject signals (delay subject signals S1 to S4).

In more detail, the delay signal generation circuit 200 includes delaycircuit 220 having plural stages of delay elements 221 (a plurality ofdelay elements 221), selectors 230 for selectively retrieving an outputsignal of one of the plural stages of delay elements 221, and a delayamount control circuit 210 for executing switching control of the delayamount for each delay element 221.

The delay circuits 220 are formed by connecting, in series, the pluralstages of delay elements 221, for which the delay amount is variably setaccording to a control voltage Vc applied thereto. There are four delaycircuits 220, each corresponding to one of the delay subject signals. Adifferent delay subject signal is input at an input terminal of each ofthe four delay circuits 220, which are parallel circuits. A signaldelayed a predetermined amount by each stage of the delay elements 221in each delay circuit 220 is output to the selector 230.

The selector 230 retrieves a delay amount setting signal output from thefirst circuit 151 shown in FIG. 1. The selector 230 selects an outputsignal from one of the plural stages of delay elements 221 in the delaycircuit 220 according to the delay amount setting signal and outputs theselected output signal as a delay signal.

The delay amount control circuit 210 controls the control voltage thatis to be applied to each stage of the delay elements 221 included in thedelay circuits 220 in a manner that a delay amount for each delayelement 221 becomes a fraction of an integer of one cycle of thereference clock signal CLK. Further, the delay amount control circuit210 switches the predetermined integer according to the specificationrelating to generation of the recording pulse.

The specification for CDs requires an accuracy of one sixteenth of acycle of a reference clock signal for a recording pulse. In comparison,the specification for DVDs requires an accuracy of one twentieth of acycle of a reference clock signal for a recording pulse. In this way,the specifications for CDs and DVDs both require a recording pulse tohave a pulse waveform set at a time interval shorter than a cycle of thereference clock signal. In the delay circuit 220, therefore, a minimumdelay amount, which is a value obtained by dividing the time period forone cycle of a reference clock signal by an integer, is used as a unittime, and signals having delay amounts varying from the delay amountcorresponding to the unit time to the delay amount corresponding to thedifference between the time period of one cycle of the reference clocksignal and the unit time are generated.

In this state, the accuracy set for a fraction of an integer of thereference clock signal differs for each specification. In other words,the value of the integer differs for each specification. Accordingly,the delay amount control circuit 210 executes switching control of thecontrol voltage Vc in a manner that the delay amount for one stage ofthe delay circuit 220 in one cycle of the reference clock signal CLK isthe delay amount corresponding to the specification.

In more detail, the delay amount control circuit 210 includes a voltagecontrolled oscillator 211 formed by connecting an inverter 211 b andplural stages of delay elements 211 a, which have the same configurationas the delay elements 221, in a ring-like manner. The delay amount foreach delay element 211 a is controlled by a control voltage inputapplied to a control terminal thereof. The delay amount control circuit210 forms a PLL circuit for locking an output signal (output frequency)of the voltage controlled oscillator 211 at a point where a delay amountfor each delay element 211 a of the voltage controlled oscillator 211becomes a fraction of an integer of one cycle of a reference clocksignal CLK. In this way, the control voltage applied to a controlterminal of each delay element 221 is set in a manner such that thedelay amount for each delay element 221 becomes a fraction of an integerof one cycle of the reference clock signal CLK.

To be more specific, in the delay amount control circuit 210, thefrequency of an output signal of the voltage controlled oscillator 211is divided by a predetermined frequency dividing ratio by a frequencydivider 222, whereas the frequency of the reference clock signal outputfrom the clock generation circuit 110 shown in FIG. 1 is divided by apredetermined frequency dividing ratio by a frequency divider 223. Thephases of the signals resulting from the frequency division by thefrequency dividers 222 and 223 are compared in a phase comparator 224. Asignal according to a phase difference detected in the phase comparator224 is output as a control voltage Vc from a low pass filter 225 (filtercircuit). Each of the frequency dividing ratios may be “1”.

The delay elements 211 a included in the voltage controlled oscillator211 and the delay elements 221 included in the delay circuit 220 willnow be described in more detail.

A voltage of a predetermined value is applied by a bias circuit 240 toeach of the delay elements 211 a and the delay elements 221. The delayamounts for each of the delay elements 211 a and the delay elements 221are controlled according to the control voltage applied to the controlterminal thereof. FIG. 3 shows the circuit configuration of each delayelement 211 a and each delay element 221.

As shown in FIG. 3, each delay element is basically formed byconnecting, in series, two stages of inverters (inverters IV1 and IV2),each of which includes a P-channel transistor TP and an N-channeltransistor TN. A current control transistor TC1 formed by a P-channeltransistor is connected between the inverters IV1 and IV2 and a powersupply potential V. A current control transistor TC2 formed by anN-channel transistor is connected between the inverters IV1 and IV2 anda ground potential. Buffer circuits B1 and B2 are provided incorrespondence to the inverters IV1 and IV2. Each of the buffer circuitsB1 and B2 is formed by a P-channel transistor TP and an N-channeltransistor TN whose gate electrodes are electrically connected to thegate electrodes of the transistors TP and TN of the corresponding one ofthe inverters IV1 and IV2.

Voltage of a predetermined value is applied to the gate terminal of thecurrent control transistor TC1 of each of the inverters IV1 and IV2 bythe bias circuit 240 shown in FIG. 2. Also, control voltage Vc isapplied to the gate terminal of the current control transistor TC2 ofeach of the inverters IV1 and IV2.

Thus, when the control voltage Vc increases, the current flowing throughthe inverters IV1 and IV2 increases, and the delay amount added to thesignal input into the delay element decreases. When the control voltageVc decreases, the current flowing through the inverters IV1 and IV2decreases, and the delay amount added to the signal input to the delayelement increases. In this way, the delay amount of the delay element iscontrolled by the level of the control voltage Vc.

An output of the inverter IV2, which is the latter stage in the delayelement, is input to the delay element of the next stage. The selector230 shown in FIG. 2, however, retrieves the output of the buffer circuitB2 of the latter stage provided in correspondence to the inverter IV2 ofthe latter stage.

The process for generating a delay signal executed by the delay signalgeneration circuit 200, which has the delay elements described abovewill now be described.

To set the delay amount for the delay element 221 as a fraction of apredetermined integer of one cycle of a reference clock signal, thecontrol unit 30 shown in FIG. 1 outputs a frequency dividing ratiosetting signal according to whether the optical disc 1 is a CD or a DVDto each of the frequency dividers 222 and 223 included in the secondcircuit 152.

In the preferred embodiment, a delay amount for one stage of the delaycircuit 220 is set to have an accuracy of one thirty-second of one cycleof the reference clock signal in the case of a CD, and is set to have anaccuracy of one fortieth of one cycle of the reference clock signal inthe case of a DVD. Accordingly, the delay circuit 220 includes the delayelements 221 of 40 stages connected in series. The voltage controlledoscillator 211 includes the delay elements 211 a of 20 stages connectedin series. Thus, a time period corresponding to one cycle of a signaloscillated by the voltage controlled oscillator 211 substantiallycoincides with delay amounts (delay times) applied to the delay elements221 of 40 stages included in the delay circuit 220.

Accordingly, the frequency dividing ratio used in the frequency divider222 and the frequency dividing ratio used in the frequency divider 223are both set at “1” when the optical disc 1 is a DVD. In this case, theoutput of the voltage controlled oscillator 211 is locked at a pointwhere the cycle of the output signal of the voltage controlledoscillator 211 and the cycle of the reference clock signal coincide witheach other. This locks the control voltage Vc. One fortieth of the cycleof the output signal of the voltage controlled oscillator 211 is thedelay amount of each delay element 211 a. Accordingly, the delay amountof each delay element 211 a is one fortieth of one cycle of thereference clock signal.

When the optical disc 1 is a CD, the frequency dividing ratio used inthe frequency divider 222 is set at “4”, and the frequency dividingratio used in the frequency divider 223 is set at “5”. In this case, theoutput of the voltage controlled oscillator 211 is locked at a pointwhere the cycle of the output signal of the voltage controlledoscillator 211 becomes five fourths of the cycle of the reference clocksignal. This locks the control voltage Vc. One fortieth of the cycle ofthe output signal of the voltage controlled oscillator 211 correspondsto a delay amount applied to each delay element 211 a. Accordingly, thedelay amount of each delay element 211 a corresponds to onethirty-second of one cycle of the reference clock signal.

When the optical disc 1 is a CD, the selection range of the output ofthe delay elements 221 of the delay circuit 220 is restricted in theselector 230. To be more specific, among the delay elements of the 40stages, the outputs of the delay elements of the 1st to 32nd stagesbecome effective for the selection, and the delay elements of the 33rdand the subsequent stages become ineffective for the selection.

In this way, by appropriately switching the frequency dividing ratio ofthe output signal of the voltage controlled oscillator 211 and of thereference clock signal with the frequency dividers 222 and 223, a delayamount for each delay element 221 is controlled to be switched to avalue suitable for each disc medium.

In the logic circuit 300 shown in FIG. 2, a recording pulse is generatedbased on the delay signals D1 to D4 output from the delay signalgeneration circuit 200 and the clock synchronization signal.

The process for generating the recording pulse in the preferredembodiment will now be described with reference to FIG. 4.

FIG. 4( b) shows one example of data modulated by the DVD encoder 120 orby the CD encoder 130. The modulated data is synchronized with edges ofthe reference clock signal shown in FIG. 4( a). The modulated data issubjected to pulse modulation based on the table data stored in theregister 151 a shown in FIG. 1. This generates the recording pulse shownin FIG. 4( c).

The recording pulse is set to correspond to each pulse of the modulateddata (from the rising edge to the fall edge of the data). The recordingpulse corresponding to each pulse of the modulated data has one or morepulses. Although FIG. 4( c) shows an example of a recording pulse thathas three pulses, the number of pulses configuring the recording pulsevaries depending on the pulse length of the modulated data.

As shown in FIG. 4( c), the rising edge and the falling edge of eachpulse that configuring the recording pulse is not necessarilysynchronized with the rising edge of the reference clock signal. This isbecause the rising edge R1 of the first pulse of the recording pulse,the falling edge F1 of the first pulse, the rising edge R2 of the secondpulse, and the falling edge Ff of the final pulse serve as parametersadjusted to appropriately record data onto the optical disc 1.

When generating the recording pulse, the rising edge R1 of the firstpulse, the falling edge F1 of the first pulse, the rising edge R2 of thesecond pulse, and the falling edge Ff of the final pulse are set usingthe four delay signals D1 to D4.

To enable these settings, delay subject signals S1 to S4 are firstgenerated in the first circuit 151 shown in FIG. 1 according to eachpulse of the modulated data, that is, according to the desired recordingpulse (FIGS. 4( d) to 4(g)). The delay subject signal S1 shown in FIG.4( d) has a pulse that rises to precede the rising edge R1 of the firstpulse by not more than one cycle of the reference clock signal. This isbecause a maximum delay amount applied by the delay circuit 220corresponds to one cycle of the clock signal. In the same manner, thedelay subject signal S2 shown in FIG. 4( e) has a pulse that falls toprecede the falling edge F1 of the first pulse by not more than onecycle of the reference clock signal. As show in FIGS. 4( d) and 4(e),the delay subject signal S1 and the delay subject signal S2 are assumedto be the same signal. The delay subject signal S3 shown in FIG. 4( f)has a pulse that rises to precede the rising edge R2 of the second pulseby not more than one cycle of the reference clock signal. Further, thedelay subject signal S4 shown in FIG. 4( g) has a pulse that falls toprecede the falling edge Ff of the final pulse by not more than onecycle of the reference clock signal.

The delay subject signals S1 to S4 and delay amount setting signalscorresponding to the delay subject signals S1 to S4 are first generatedin the first circuit 151 shown in FIG. 1. Based on these signals, delaysignals D1 to D4 (FIGS. 4( h) to 4(k)) are then generated in the delaysignal generation circuit 200 shown in FIG. 2. The delay signal D1 shownin FIG. 4( h) rises in synchronization with the rising edge R1 of thefirst pulse. The delay signal D2 shown in FIG. 4( i) falls insynchronization with the falling edge F1 of the first pulse. The delaysignal D3 shown in FIG. 4( j) rises in synchronization with the risingedge R2 of the second pulse. Further, the delay signal D4 shown in FIG.4( k) falls in synchronization with the falling edge Ff of the finalpulse.

In the second circuit 152 shown in FIG. 1, the recording pulse isgenerated using the delay signals D1 to D4. To be more specific, asshown in FIG. 4 (l), an AND signal of the delay signal D1 and the delaysignal D2 is generated. As shown in FIG. 4( m), an exclusive OR signalof the delay subject signal S3 and the delay signal D3 is generated.Further, as shown in FIG. 4( n), an AND signal of the signal shown inFIG. 4( m) and the delay signal D4 is generated. Using an OR signal ofthe signal shown in FIG. 4( l) and the signal shown in FIG. 4( n), therecording pulse shown in FIG. 4( c) is generated.

The process for generating the recording pulses shown in FIGS. 4( l) to4(n) schematically represents the recording pulse generation processexecuted in the second circuit 152. In the actual process, the recordingpulse is generated using, in addition to the delay subject signals, aclock synchronization signal and the like output from the first circuit151.

The preferred embodiment described above has the following advantages.

(1) The delay amount control circuit 210 controls the control voltage VCapplied to each delay element 221 of the delay circuits 220 in a mannerthat a delay amount for each delay element 221 becomes a predeterminedfaction of an integer of one cycle of the reference clock signal CLK.Also, the delay amount control circuit 210 switches the predeterminedinteger according to the specification relating to generation of therecording pulse. This enables the same delay circuit 220 to be used whenthe disc medium onto which data is to be recorded is a CD and when thedisc medium is a DVD. Thus, enlargement of the circuit scale of thedelay signal generation circuit 200 (write strategy circuit 150) issuppressed in an optimal manner.

(2) The delay amount control circuit 210 is formed as a PLL circuit thatlocks the output signal of the voltage controlled oscillator 211 at apoint where the delay amount for each delay element 211 a becomes apredetermined fraction of one cycle of the reference clock signal CLK.The voltage controlled oscillator 211 is formed by connecting the pluralstages of delay elements 211 a, which having the same configuration asthe delay elements 221, in a ring-like manner. This simplifies theconfiguration of the delay amount control circuit 210 that generates thecontrol voltage Vc.

(3) The first circuit 151 of the write strategy circuit 150 includes theregister 151 a for storing the table data defining the pulse modulationmode of data subject to pulse-modulation according to specificationsthat differ from each other. Therefore, by externally designating thetable data, the recording pulse is generated both when data is to berecorded onto a DVD and when data is to be recorded onto a CD. Due tothe employment of the register, an increase in the circuit scale of thewrite strategy circuit is suppressed compared with when all the tabledata is stored within the write strategy circuit. Also, by changing thetable data stored in the register, a recording pulse that is inaccordance with the specification of a disc medium other than a DVD anda CD may also be generated. In this way, the write strategy circuit hasversatility.

The above preferred embodiment may be modified as described below.

The clock generation circuit 110 for generating a reference clock signalis not limited to the above configuration. For example, the circuit thatgenerates a clock signal for CDs may generate the reference clock signalbased on the wobble signal read from an optical disc in lieu of theoscillator.

The rotation of an optical disc when recording data does not have to becontrolled using the constant linear velocity method and may becontrolled using the constant angular velocity method. In this case, areference clock signal is generated based on a signal retrieved as alaser reflection from a rotation-controlled optical disc controlled inthe same manner as in the PLL circuit 112.

The quantity of the stages of delay elements in the voltage controlledoscillator 211 may be one.

The delay elements 211 a and the delay elements 221 are not limited tothe configuration exemplified in FIG. 3. Further, the delay elements 211a and the delay elements 221 are not limited to circuits that delay aninput signal and output a delayed signal, but may be an inverter thatdelays an input signal and outputs a logically inverted signal. In thiscase, an inverter may be provided at the output of the selector 230, andthe voltage controlled oscillator may include an odd number ofinverters.

The delay amount control circuit 210 is not limited to the configurationexemplified in FIG. 2.

The write strategy circuit is not limited to a configuration functioningonly to generate a recording pulse as a timing signal. For example, thewrite strategy circuit may function to generate a sampling signal, whichis generated by adding a predetermined delay to the rising or fallingedge of a reference clock signal and used to control a recording laseroutput, as a timing signal. This is also effective when applying a delaysignal generator according to the present invention for generating adelay signal through processing executed by a delay signal generationcircuit.

The optical disc is not limited to those exemplified in the abovepreferred embodiment and may be any disc medium. In such a case, the useof a delay signal generated by the delay signal generation circuit iseffective when the laser irradiation mode is controlled based on two ormore specifications.

1. A delay signal generator generating a plurality of delay signalsincluding a first delay signal used in recording data to a first-typedisc media and a second delay signal used in recording data to asecond-type disc media, the delay signal generator comprising: a delaycircuit for delaying an input signal in a stepped manner and including aplurality of series-connected first delay elements, each controlling adelay amount in accordance with a control voltage; a delay amountcontrol circuit, connected to the delay circuit, for generating thecontrol voltage and supplying the plurality of first delay elements withthe control voltage; and a selector, connected to the delay circuit, forselecting an output of one of the plurality of first delay elements andgenerating a delay signal with a predetermined delay amount; wherein thedelay amount control circuit includes: a voltage controlled oscillatorhaving a plurality of second delay elements connected in a ring-likemanner, the second delay elements each having the same configuration asthe first delay elements, and the quantity of the second delay elementsbeing based on the quantity of the first delay elements; a firstfrequency divider, connected to the voltage controlled oscillator, forreceiving a frequency dividing ratio setting signal generated dependingon the type of the disc media and for dividing the frequency of anoutput signal of the voltage controlled oscillator by a first frequencydividing ratio according to the frequency dividing ratio setting signalto generate a first frequency-divided signal; a second frequency dividerfor receiving the frequency dividing ratio setting signal and apredetermined reference clock signal generated depending on the type ofthe disc media and for dividing the frequency of the predeterminedreference clock signal by a second frequency dividing ratio according tothe frequency dividing ratio setting signal to generate a secondfrequency-divided signal; a phase comparator, connected to the first andsecond frequency dividers, for comparing a phase of the firstfrequency-divided signal and a phase of the second frequency-dividedsignal to generate a comparison signal; and a filter circuit, connectedto the phase comparator, for generating the control voltage in responseto the comparison signal; wherein the delay amount control circuitchanges the delay amount for one of the first delay elements included inthe delay circuit by changing a frequency dividing ratio rate that is aratio of the second frequency dividing ratio relative to the firstfrequency dividing ratio.
 2. The delay signal generator according toclaim 1, wherein: the delay amount control circuit generates a firstcontrol signal for generating a first delay signal when dividing thefrequency of the reference clock signal by m, where m is a naturalnumber, and generates a second control signal for generating a seconddelay signal when dividing the frequency of the reference clock signalby n, where n is a natural number and n<m; the delay circuit includes anm number of first delay elements; the delay amount control circuit setsa delay amount for one of the first delay elements included in the delaycircuit at 1/n of a cycle of the reference clock signal when the seconddelay signal is generated; and the selector selects an output of one ofan n number of the first delay elements when the second delay signal isgenerated.
 3. The delay signal generator according to claim 2, wherein:the voltage controlled oscillator includes an m/2 number of the seconddelay elements; and the delay amount control circuit sets the frequencydividing ratio at m/n when the second delay signal is generated.
 4. Thedelay signal generator according to claim 1, wherein: the selector has aselection range of the output of the first delay elements, the selectionrange being variable depending on the type of the disc media.
 5. Arecording pulse generator for retrieving modulated data that has beensubjected to a predetermined modulation process and generating recordingpulses including a first recording pulse used in recording data to afirst-type disc media and a second recording pulse used in recordingdata to a second-type disc media, the recording pulse generatorcomprising: a plurality of delay circuits, each of which delays an inputsignal in a stepped manner, includes a plurality of series-connectedfirst delay elements, and controls a delay amount in accordance with acontrol voltage; a delay amount control circuit, connected to theplurality of delay circuits, for generating the control voltage andsupplying the plurality of first delay elements included in each delaycircuit with the control voltage; a plurality of selectors, eachconnected in correspondence with one of the plurality of delay circuits,each of the selectors selecting an output of one of the plurality offirst delay elements included in the corresponding delay circuit andgenerating a delay signal with a predetermined delay amount; and a logiccircuit, connected to the plurality of selectors, for logicallysynthesizing the delay signal of each selector to generate a recordingpulse; wherein the delay amount control circuit includes: a voltagecontrolled oscillator including a plurality of second delay elements,each having the same configuration as the first delay elements and beingconnected in a ring-like manner, the quantity of the second delayelements being based on the quantity of the first delay elements; afirst frequency divider, connected to the voltage controlled oscillator,for receiving the frequency dividing ratio setting signal generateddepending on a type of the disc media and for dividing the frequency ofan output signal of the voltage controlled oscillator by a firstfrequency dividing ratio according to the frequency dividing ratiosetting signal and generating a first frequency-divided signal; a secondfrequency divider for receiving the frequency dividing ratio settingsignal and a predetermined reference clock signal generated depending onthe type of the disc media and for dividing the frequency of apredetermined reference clock signal by a second frequency dividingratio according to the frequency dividing ratio setting signal andgenerating a second frequency-divided signal; a phase comparator,connected to the first and second frequency dividers, for comparing aphase of the first frequency-divided signal and a phase of the secondfrequency-divided signal to generate a comparison signal; and a filtercircuit, connected to the phase comparator, for generating the controlvoltage in response to the comparison signal; wherein the delay amountcontrol circuit changes the delay amount for one of the first delayelements included in each delay circuit by changing a frequency dividingratio rate that is a ratio of the second frequency dividing ratiorelative to the first frequency dividing ratio, wherein the delay amountcontrol circuit receives a frequency dividing ratio setting signalgenerated depending on the type of the disc media and changes a delayamount for one of the first delay elements included in each delaycircuit by changing the control voltage in accordance with the frequencydividing ratio setting signal.
 6. The recording pulse generatoraccording to claim 5, wherein: when the frequency of the reference clocksignal is divided by m, where m is a natural number, the logic circuitgenerates a first recording pulse signal having a pulse width controlledin accordance with that frequency dividing ratio, and when the frequencyof the reference clock signal is divided by n, where n is a naturalnumber and n<m, the logic circuit generates a second recording pulsesignal with a pulse width controlled according to that frequencydividing ratio; each of the plurality of delay circuits includes an mnumber of first delay elements; the delay amount control circuit sets adelay amount for one of the first delay elements included in each delaycircuit at 1/n of a cycle of the reference clock signal when the secondrecording pulse signal is generated; and each selector selects an outputof one or an n number of the first delay elements when the secondrecording pulse signal is generated.
 7. The recording pulse generatoraccording to claim 6, wherein: the voltage controlled oscillatorincludes an m/2 number of second delay elements; and the delay amountcontrol circuit sets the frequency dividing ratio rate at m/n when thesecond recording pulse is generated.